The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to solder interconnect structures with non-wettable sidewalls and methods of manufacturing the same.
Copper pillars are a chip-to-chip interconnect technology used to enhance electromigration performance, to reduce the pitch of interconnects, and to provide for a larger gap, or standoff, between individual chips for underfill flow over conventional solder controlled collapse chip connections (C4 connections). In copper pillar technology, a small amount of solder is still required to connect and join the copper pillars of one chip to a pad of another chip or substrate. However, it is difficult to prevent the solder from wetting to the sidewalls of copper pillars. This sidewall wetting may reduce the gap or standoff, therefore limiting underfill flow between the one chip and the other chip or substrate. In addition, the sidewall wetting can sometimes lead to solder bridging or shorting between two adjacent copper pillars in tight pitch applications. Typically, the pitch between copper pillars must be increased to prevent or alleviate the bridging or shorting.